The present invention relates to a processor circuit comprising a first processor which can be coupled to a first input/output of a memory circuit. The processor circuit includes; a peripheral circuit which can be coupled to the first processor. A second input/output of the memory circuit may be coupled to a second processor.
Such a processor circuit is disclosed in U.S. Pat. No. 4,620,118. The processor circuit described therein comprises the memory circuit, which consists of a memory (random-access memory or RAM), a multiplexer (MUX) coupled thereto, a first switching port (LATCH-1) which is coupled to the MUX and is connected to the first processor, and a second switching port (LATCH-2) which is coupled to the MUX and is connected to the second processor. As a result of using the MUX and the two LATCHES, the RAM is transformed into a so-called quasi-dual port RAM (QDPR) or into a memory circuit having a first input/output and a second input/output. The two processors can communicate with one another via such a memory circuit, a conflict being avoided by using a so-called contention-resolving circuit (CRC) coupled to both processors and the MUX.
Such a known processor circuit is disadvantageous because it has little flexibility because it is insufficient for test purposes and has insufficient back-up facilities at its disposal.